1. Field of the Invention
The present invention relates to a semiconductor memory device, such as a dynamic RAM, and in particular to a semiconductor memory device which has a collector-grounded transistor and which prevents the leakage of an electric charge from a memory cell.
2. Related Arts
A dynamic RAM, which has a number of memory cells, each of which is constituted by a cell transistor and a cell capacitor, is widely employed as a large capacity high-speed memory. For such a memory device, a memory cell area wherein a plurality of memory cells are formed and an area wherein peripheral circuits are formed are provided at the surface of a semiconductor substrate. An MOS cell transistor, which is connected to a bit line and to a word line, and a cell capacitor, which is connected to the cell transistor, are formed in the memory cell area. A CMOS circuit, and a reference voltage generator, which employs a PNP bipolar transistor, are formed in the peripheral circuit formation area.
To provide a CMOS circuit as a peripheral circuit, for example, a P-type well region and an N-type well region are formed in a P-type semiconductor substrate, and an N-type channel MOS transistor and a P-type channel MOS transistor are formed in each well region. In the memory cell area, a back bias voltage, which is lower than the ground voltage, is applied to the channel region, so that a high threshold voltage is set for the cell transistor to reduce current leakage in the OFF state. Therefore, the memory cell area is formed in a P-type well region which is separated from a well region wherein the peripheral circuits are formed, and the back bias voltage is applied to the P-type well region.
FIG. 1 is a cross-sectional view of the structure of a conventional semiconductor memory device. A P-type well region P-WellA and an N-type well region N-WellB are formed in a P-sub semiconductor substrate 10. Although not shown, an N-type channel MOS transistor and a P-type channel MOS transistor are also formed in each well region. A P-type emitter region 12 and an N-type base contact region 13 are formed close to the P-type well region P-WellA in the N-type well region N-WellB, and a P-type collector contact region 14 is formed in the P-type well region P-WellA, so as to form a lateral PNP transistor. Such a lateral PNP transistor is employed as a reference voltage generator, as will be described later. In this case, the ground voltage is set for the collector contact region 14, and accordingly, the ground voltage is maintained for the P-type substrate 10.
A P-type well region P-WellC, which serves as the memory cell area, is formed in the N-type well region N-WellB, and is electrically separated from the P-type substrate 10. Therefore, in the P-type well region P-WellC a back bias voltage V.sub.BB is maintained, which is lower than the ground voltage. A drain region 15 and a source region 16 for a cell transistor Tc are formed in the P-type well region P-WellC, and a back bias voltage V.sub.BB is applied to the P-type well region P-WellC. A cell capacitor Qc is connected to the source region 16 of the cell transistor Tc.
In the conventional structure in FIG. 1, the P-type well region P-WellC, wherein a memory cell is provided, is formed in the N-type well region N-WellB using the ion implantation method and the thermal diffusion method. Therefore, the impurity concentration of the P-type well region P-WellC can not be very high. As a result, between the N-type source region 16 and the P-type well region P-WellC an energy barrier at a PN junction can not be set high, and the occurrence of current leakage can not be prevented.
The storage of information in a memory cell is performed whether or not an electric charge is accumulated in the cell capacitor Qc. Therefore, current leakage between the source region 16 and the P-type well region P-WellC results in the loss of stored information during a refresh cycle. In order to prevent the loss of data, the refresh cycle must be shortened.